The present invention relates to content addressable memory (CAM) arrays. More specifically, the present invention relates to dynamic random-access-memory-based (DRAM-based) CAM arrays.
Conventional read-write or xe2x80x9crandom accessxe2x80x9d memory (RAM) arrays include RAM cells arranged in rows and columns, and addressing circuitry that accesses a selected row of RAM cells using address data corresponding to the physical address of the RAM cells. That is, data words stored in the rows of conventional RAM cells are accessed by applying address signals to the RAM array input terminals. In response to each unique set of address signals, a RAM array outputs a data word that is read from a portion of the RAM array designated by the address.
Unlike conventional RAM arrays, content addressable memory (CAM) arrays include memory cells that are addressed in response to their content, rather than by a physical address within a RAM array. Specifically, a CAM array receives a data value that is compared with all of the data values stored in the rows of the CAM array. In response to each unique data value applied to the CAM array input terminals, the rows of CAM cells within the CAM array assert or de-assert associated match signals indicating whether or not one or more data values stored in the CAM cell rows match the applied data value. CAM arrays are useful in many applications, such as search engines.
Similar to conventional RAM devices, CAM devices can either be formed utilizing dynamic random access memory (DRAM) cells, in which data values are stored using capacitors, or formed utilizing static random access memory (SRAM) cells, in which data values are stored using bistable flip flops.
FIG. 1(A) is a circuit diagram showing a conventional dynamic-based (DRAM-based) CAM cell 10, which includes a pair of one-transistor (1T) DRAM cells 12 and 16, and a four-transistor comparator circuit 14 made up of transistors Q2 through Q6. DRAM cell 12 includes transistor Q1 and a capacitor structure C1, which combine to form a storage node a that receives a data value from bit line BL1 during write operations, and applies the stored data value to the gate terminal of transistor Q2 of comparator circuit 14. Transistor Q2 is connected in series with transistor Q3, which is controlled by a data signal transmitted on inverted data line D1# (the xe2x80x9c#xe2x80x9d is used herein to designate complement), between a match line (MATCH) and a discharge line (DISCHARGE). A second DRAM cell 16 includes transistor Q3 and a capacitor structure C2, which combine to form a storage node b that receives a data value from bit line BL2, and applies the stored data value to the gate terminal of transistor Q4 of comparator circuit 14. Transistor Q4 is connected in series with transistor Q5, which is controlled by a data signal transmitted on inverted data line D1#, between the match line and the discharge line.
During a data write operation (or during the write phase of a refresh operation), a data value to be stored is written to dynamic storage nodes a and b by applying appropriate voltage signals (e.g., VCC or ground) on bit lines BL1 and BL2, and then applying a high voltage signal on word lines WL1 and WL2. The high voltage on word lines WL1 and WL2 turn on transistor Q1 and Q2, thereby passing the voltage signals to dynamic storage nodes a and b. Because the voltage signals are stored using capacitors Cl and C2, the stored data value decays over time, thereby requiring refresh circuitry that periodically reads and rewrites (refreshes) the stored data value before it is lost.
The data value stored at storage nodes a and b is applied to the gate terminals of transistors Q2 and Q5 of comparator circuit 14. Comparator circuit 14 is utilized to perform match (comparison) operations by precharging a match line M and transmitting an applied data value on data lines D1 and D1# to the gate terminals of transistor Q3 and Q6, respectively. A no-match condition is detected when match line M is discharged to ground through the signal path formed by transistors Q2 and Q3, or through the signal path formed by transistors Q5 and Q6. For example, when the stored data value at node a and the applied data value transmitted on data line D1# are both logic xe2x80x9c1xe2x80x9d, then both transistors Q2 and Q3 are turned on to discharge match line M to the discharge line (e.g., ground). When a match condition occurs, match line M remains in its pre-charged state (i.e., no signal path is formed by transistors Q2 and Q3, or transistors Q5 and Q6).
A problem with DRAM-based CAM cell 10 arises because the voltage signal (charge) stored at storage nodes a and b are directly applied to (shared with) bit lines BL1, and BL2, respectively, during read operations. Specifically, the charge stored at storage nodes a and b must be strong enough to pass through access transistors Q1 and Q4 and swing the voltage levels on bit lines BL1 and BL2 such that the stored data value can be read, for example, by a sense amplifier (not shown) connected to bit lines BL1 and BL2. To provide this sufficient capacitance, capacitor structures C1 and C2 are often constructed using a special multi-layer polysilicon fabrication process that significantly increases fabrication time and expense. In addition, because the size of these capacitor structures is limited, the length of bit lines BL1 and BL2 must be limited to avoid excessively large bit line capacitances, thereby minimizing the number of CAM cells in each column of a DRAM-based CAM array. That is, the length and, hence, the capacitance of bit lines BL1 and BL2 increases with the number of DRAM CAM cells that are connected to these lines. Specifically, the voltage swing on a bit line is inversely proportional to bit line capacitance (i.e., length). When the bit line is too long (i.e., has too high of a capacitance), then the bit line voltage swing is too small to read. Because the length of the bit lines is limited, so too are the number of DRAM cells in each column that are connected to the bit line. By limiting the number of DRAM CAM cells in each column, the number of independent blocks of DRAM memory cells is increased, thereby requiring more space for control circuitry and increasing the overall size and cost of the DRAM CAM circuit. Finally, conventional DRAM-based CAM cell 10 is limited in that a read operation can be disturbed by a simultaneous match operation performed by comparator circuit 14. When conventional DRAM cells 12 and 16 are read, the read data values are typically transmitted to associated bit lines during xe2x80x9cquietxe2x80x9d periods in which switching noise in a DRAM array does not cause a loss of the read data values. However, by allowing simultaneous match operations during the read phase of the refresh operation, it is possible to lose the read data values.
FIGS. 1(B) and 1(C) are circuit diagrams showing conventional SRAM-based CAM cells 20 and 30, respectively. In general SRAM-based CAM cells require more transistors than DRAM-based CAM cells, and are therefore typically much larger than DRAM-based CAM cell 10 (see FIG. 1(A)). In addition, SRAM-based CAM arrays typically consume more power than DRAM-based CAM arrays. However, SRAM-based CAM cells overcome the charge sharing problems associated with DRAM-based CAM cells by utilizing bistable flip flops, which are able to store data values without the refresh operation required by DRAM cells. Further, even when a stored data value is read, the bistable flip flops transmit a current onto an adjoining bit line that, over time, generates enough charge to swing the bit line to indicate the stored data value. This current-over-time approach allows SRAM-based CAM arrays to include much longer bit lines (i.e., many more SRAM cells per bit line) because bit line swing can be achieved for any bit line length, given enough current and enough time.
FIG. 1(B) shows a twelve transistor (12T) SRAM-based CAM cell 20 including two four-transistor (4T) SRAM cells 22 and 26 that apply stored data values to comparator circuit 14, which performs match operations in the manner described above with reference to FIG. 1(A). SRAM cell 22 includes access transistors Q11 and Q13 for passing data values from bit lines BL1 and BL1# to storage nodes a and a#, respectively, which apply the stored data values to pull-down transistors Q12 and Q14, respectively, thereby producing a bistable structure. Note that storage nodes a and a# are connected to VCC via resistors R1 and R2, respectively. Similarly, SRAM cell 26 includes access transistors Q15 and Q17 for passing data values from bit lines BL2 and BL2# to storage nodes b and b#, respectively, which are connected to system voltage VCC by resistors R3 and R4, and apply the stored data values to pull-down transistors Q16 and Q16, respectively.
In addition to the general problems associated with SRAM-based CAM cells mentioned above, a particular problem associated with 12T SRAM-based CAM cell 20 is that, similar to capacitor structures C1 and C2 of DRAM-based CAM cell 10 (discussed above), resistors R1 through R4 require special (i.e., non-standard) fabrication processes. These special fabrication processes significantly increase the time and cost needed to fabricate devices including SRAM-based CAM cell 20.
FIG. 1(C) shows a sixteen transistor (16T) SRAM-based CAM cell 30 including two six-transistor (6T) SRAM cells 32 and 36 that apply stored data values to comparator circuit 14. SRAM cell 32 utilizes series-connected pairs of p-channel transistors and n-channel transistors (i.e., P21 and N21, and P22 and N22) to provide pull-up and pull-down latching a data value at storage nodes a and a#, and a pair of access transistors N23 and N24 for passing the data value to storage nodes a and a# during write operations. Similarly, SRAM cell 26 utilizes series-connected pairs of p-channel transistors and n-channel transistors (i.e., P25 and N25, and P26 and N26) to latch a data value at storage nodes b and b#, and a pair of access transistors N27 and N28 for passing the data value to storage nodes b and b# during write operations.
Although 16T SRAM-based CAM cell 30 avoids the need for the resistors used in 14T SRAM-based CAM cell 20 (discussed above), the use of different transistor types (e.g., p-channel transistor P21 and n-channel transistor N21) require special layout considerations that complicate the manufacturing process and significantly increase the size of a CAM structure including several 16T SRAM-based CAM cells 30.
Accordingly, what is needed is a CAM cell that provides the size advantages of a DRAM CAM cell and the performance benefits of an SRAM CAM cell, and avoids the need for special fabrication processing and layout considerations.
The present invention is directed to DRAM-based CAM cells that overcome the problems associated with conventional CAM cells by utilizing three-transistor (3T) or four-transistor (4T) DRAM cells to store data values. Although larger than conventional 1T DRAM cells, the intrinsic capacitance of each 3T or 4T DRAM cell avoids the need for the discrete capacitor structures typically required in the 1T DRAM cells, thereby simplifying the fabrication process. Further, read operations are performed without disturbing the stored data value by, for example, applying the stored data value to the gate terminal of a pull-down transistor and detecting the operating state (i.e., turned on or turned off) of the pull-down transistor, thereby avoiding the charge sharing problems associated with 1T DRAM cells, and increasing bit line lengths (i.e., array size). Accordingly, the present invention provides CAM cells that combine cell size and power consumption characteristics similar to conventional DRAM-based CAM cells with performance and array size characteristics associated with conventional SRAM-based CAM cells, and avoids the need for special fabrication processes.
In accordance with a first specific embodiment of the present invention, a ten transistor (10T) DRAM-based ternary CAM cell includes a pair of 3T DRAM cells for storing first and second data values, and a four transistor comparator circuit that discharges a match line when either of the first and second data values fails to match and applied data value (and its complement) provided from an external source. Each 3T DRAM cell includes a write (first) transistor connected between a write (first) bit line and a storage node of the 3T DRAM cell, and a pull-down (second) transistor connected in series with a read (third) transistor between a read (second) bit line and ground. A gate terminal of the pull-down transistor is connected to the storage node, which is also connected to a first input terminal of the comparator circuit. The capacitance of the storage node is produced by the metal lines and polysilicon structures connecting the write transistor and the pull-down transistor to the first input terminal of the comparator circuit. Similar to a conventional 1T DRAM cell, a data value is written to the storage node of a selected 3T DRAM cell by turning on the write transistor and transmitting the data value from the write bit line to the storage node. However, instead of disturbing the stored data value during read operations, as in conventional 1T DRAM cells, the stored data value is indirectly xe2x80x9creadxe2x80x9d by detecting the operating state (i.e., turned on or turned off) of the pull-down transistor, which is controlled by the stored data value. When the stored data value is in a first logic state, (e.g., logic xe2x80x9c1xe2x80x9d or high), the pull-down transistor is turned on, and the read bit line is pulled to ground through the pull-down transistor. Conversely, when the stored data value is in a second logic state (e.g., logic xe2x80x9c0xe2x80x9d or low), the pull-down transistor remains turned off, and the read bit line does not change. In either case, the data value stored by the 3T DRAM cell is not disturbed, thereby allowing a simultaneous comparison operation using the comparator circuit according to known techniques.
In accordance with a second specific embodiment of the present invention, a twelve transistor (12T) ternary CAM cell includes a pair of 4T DRAM cells for storing data values, and a four-transistor comparator circuit. Each 4T DRAM cell includes a first access transistor connected between a first bit line and a primary storage node, a second access transistor connected between a second bit line and an inverted (secondary) storage node, a first pull-down transistor connected between the inverted storage node and ground and having a gate terminal connected to the primary storage node, and a second pull-down transistor connected between the primary storage node and ground and having a gate terminal connected to the secondary storage node. Refresh operations are performed in a single step by turning on the first and second access transistors and transmitting high voltages on the first and second bit lines, thereby simplifying the control circuitry needed to drive a CAM array incorporating the 12T ternary DRAM cell.
In accordance with a third specific embodiment of the present invention, a nine, eleven, or twelve transistor quad CAM cell includes a single 4T DRAM cell for storing data values, a four transistor comparator circuit, and a one, three or four transistor masking DRAM cell. The 4T DRAM cell is similar to that used in the second embodiment (described above), but relatively high operating voltage is required to selectively store logic high data values in the primary and secondary storage nodes, which are connected to the gate terminals of first and second transistors in the comparator circuit. The first and second transistors of the comparator circuit have relatively thick gate oxides to support the relatively high gate voltages applied from the storage nodes, and to pass applied data values to the gate of a third transistor, which is connected in series with a fourth transistor controlled by the masking DRAM cell between match and discharge lines. The masking DRAM cell is utilized to perform xe2x80x9cdon""t carexe2x80x9d operations while allowing the 4T DRAM cell to store original data values.
In accordance with a fourth specific embodiment of the present invention, a ten, twelve, or thirteen transistor quad CAM cell includes a single 4T DRAM cell for storing data values, a five transistor comparator circuit, and a one, three or four transistor masking DRAM cell. Although larger than the quad CAM cell of the third embodiment, the fourth embodiment avoids the need for transistors having thick gate oxides and relatively high operating voltages, thereby simplifying the fabrication process.